1. Field of the Invention
The invention relates generally to a package structure of chip and the package method thereof. In particular, the invention relates to a package structure of chip with more level surface and less height and the package method thereof.
2. Description of the Prior Art
With the rapid improvement of semiconductor technology, there are more and more requirements on the functions, portability and compact sizes for computers and telecommunication products. Accordingly, the manufacturers of chip package develop technology to produce the products with high power, high integrity, light and small size. Moreover, for electronics packaging, there are higher requirements on reliability and heat dissipation to be capable of transmitting signals and energy, providing good path of heat dissipation, protecting and supporting.
It is a trend to produce package elements of semiconductor with compact sizes, rapid speed and high integrity. However, the power consumption becomes a heavy load. Thus, it is an important issue on the heat dissipation for package elements.
Nowadays in processing printed circuit boards, each element is attached on the printed circuit board with soldering. Thus, when attached any element, the printed circuit board needs a well level surface to meet the high reliability of electrical element.
Accordingly, it is important to provide an improved package structure of chip and the formation thereof.